Silicon Odometers: On-Chip Test Structures for Monitoring Reliability Mechanisms and Sources of Variation

The aggressive down-sizing of device dimensions and voltage margins has left little room for transistor degradation, so in addition to dealing with PVT variations, a detailed understanding of numerous aging processes generally studied by device scientists is needed at the circuit and system levels. In this paper, we describe a number of circuit methods to efficiently monitor accelerated device degradation due to bias temperature instability (BTI), as well as time dependent gate dielectric breakdown (TDDB). The measurement schemes presented here can also be applied to monitor spatial or temporal variations affecting chip performance. Results from such sensors can be used to gather process information, verify existing degradation models, or trigger real-time on-chip adjustments during product usage.